A 25Gb/s RX front-end with multi-stage linear equalizer and 3-tap speculative DFE in 65nm CMOS technology

This work proposes a RX front-end structure, which is used for channel equalization of 25Gb/s high-speed links. design includes two parts, linear equalizer and decision feedback equalizer. Linear consists the variable gain amplifier, continuous-time output buffer, provide 19dB peaking around Nyquist frequency. The half-rate with one speculative tap cascaded after buffer to eliminate residual inter-symbol interference. circuit layout occupies an area 0.005mm2 designed in 65nm CMOS, power consumption 96mW under 1.2V supply. equalize FR-4 backplane channel, insertion loss reaches 35dB at 12.5GHz. result shows that both voltage margin time receiver signal reach 171mV 0.61UI BER 10-12, respectively.